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Calibre
Calibre® is the overwhelming market share leader and the industry standard for IC physical verification, due to the outstanding performance, accuracy and reliability of Calibre products. Over the last two years, Calibre nmDRC™ has reduced average DRC runtime by a factor of five, while Calibre's innovative Hyperscaling and MTFlex™ technologies have cut memory requirements in half. Calibre nmDRC also reduced overall cycle time with incremental DRC, which allows designers to make DRC runs in parallel. As DRC violations are reported, designers can immediately fix and recheck just the affected areas, while the initial DRC run continues.
Catapult
Generate Correct-by-Construction, High-Quality RTL,10-100x Faster. Catapult C Synthesis is a High Level Synthesis tool for ASIC and FPGA hardware designers of wireless, video, and image processing equipment who need to deliver optimal implementations with aggressive time-to-market requirements. By enabling designers to focus on the functional intent of their algorithms, Catapult C Synthesis reduces testbench complexity for both algorithm validation and verification.
Clock Domain Crossing (CDC)
Highly Automated solution for Clock Domain Crossing Verification. Includes Static, Dynamic and Formal methods in one engine.
- Automatically identifies all clock groups, derived and gated clocks in the design
- Supports structured, ad-hoc, and user-defined synchronization styles
- Identifies missing synchronization and incorrect synchronization
- Generates CDC protocol monitors for all signals that cross clock domains
- Detects re-convergent CDC signals in the design
DX Designer
Industry standard for schematic entry. Today's electronics product designers are under increasing pressure to deliver next-generation products in shorter time spans and at lower costs. To meet new product introduction windows, the resolution of issues such as technology choices, form, fit, function, component availability, cost, and scheduling must rely increasingly on communication and planning.
Expedition
The Expedition Enterprise flow is tailored for the mid-sized to large enterprise organizations and for systems design groups with pervasive use of leading edge PCB or high speed technologies. This tightly integrated systems design solution is composed of the industry's most advanced design and analysis functionality in an environment of constraint, library and design data management.
FormalPRO
FormalPro™ is the Mentor Graphics solution for gate-level regression testing of ASICs and ICs of 100,000 gates or more. FormalPro uses static formal verification techniques to prove that a design is functionally identical to its golden reference. This technique is orders of magnitude faster than traditional gate-level simulation. Designs that take days or even weeks to simulate with gate-level simulation can be verified in hours or even minutes using FormalPro. For designs greater than 100,000 gates, FormalPro is an essential verification tool in an ASIC design flow.
HyperLynx
The HyperLynx® suite enables engineers to quickly and accurately analyze and eliminate signal integrity, power integrity and EMI problems early in the design cycle. These simulation tools come ready to use in virtually any design flow and offer unprecedented time-to-results, improving productivity, reducing development and product costs, and increasing product performance.
I/O Designer
I/O Designer offers a unique process for moving through the design flow, from the top level HDL description to the PCB level symbol, as well as to the physical pin information necessary for the FPGA place and route tools.
ModelSim
High Performance HDL Simulator. Verilog, VHDL and the only single kernel mixed VHDL and Verilog simulator.
PADS 9.0 Suites
Mentor Graphics has combined the expansive capabilities of the PADS product line into a series of affordable PADS Suites. Mentor Graphics, the world's number one provider of PCB design solutions, has combined the expansive capabilities of the PADS® product line into a series of affordable PADS Suites. These suites have just the right mix of technology necessary for complex PCB design, yet they can be supplemented with a variety of add-on capabilities should your needs change.
PADS Layout
PADS Layout is Mentor's Desktop Solution for PCB design. PADS Layout gives you advanced rules-driven design for complex printed circuit boards. PADS Layout integrates seamlessly with the rest of PADS PCB Design Solutions, making PADS Layout part of a complete, integrated flow for design definition, analysis, planning, and layout. Add-on modules for design variant creation, advanced packaging, design-for-test, and more, enable PADS Layout to expand to meet future needs. In addition, PADS Layout offers seamless integration with Mentor Graphics' HyperLynx® tool suite, the industry's choice for signal integrity accuracy and ease of use.
Precision
Next Generation FPGA Synthesis Technology. Easy to use and excellent QoR. Precision RTL Plus offers an improved way of designing FPGAs and dramatically increasing designer productivity. This latest addition to the Precision family of products provides several industry-first capabilities that enable every designer, regardless of level of expertise, to reach timing closure faster, minimize the impact of design changes, and make efficient use of FPGA embedded blocks.
Questa
Questa is Mentor Graphic's Advanced Verification Environment and is the only integrated verification platform that can improve quality, productivity, and predictability for any verification flow. Supports System Verilog natively along with System C.
Questa ADMS
The Mentor Graphics Questa ADMS™ simulator gives designers a comprehensive environment for verifying complex analog/mixed-signal (AMS) System-on-Chip (SoC) designs. ADMS combines four high performance simulation engines in one efficient tool: Eldo™ for analog large-signal and frequency domain simulations, ModelSim® for digital simulations, Mach™ for fast transistor-level simulations and Eldo-RF™ for modulated steady state simulation. ADMS is fully integrated with the Mentor Graphics Design Architect-IC™ (DAIC) tool, the Cadence® Analog Design Environment, and the ModelSim graphical interface. The CommLib™ QuickStart™ library of essential telecommunication blocks jumpstarts your development of system level designs and exploration of architectural variations. The TCL scripting language enables batch control of the simulation.
Silicon Test and Yield Analysis
Mentor delivers highest quality silicon test and failure analysis tools to ensure that each device produced will be free of defects before delivery. Effective test development tools achieve these quality targets while maintaining profitability with lower test costs.